Staff Engineer – LEC / CLP (Logical Equivalence & Low Power Convergence)

Role Overview

As a Staff Engineer - LEC/CLP, you will play a key role in ensuring functional correctness and low-power intent integrity across the design lifecycle. You will be responsible for equivalence checking as well as validating UPF/CPF-based low-power implementations, ensuring seamless convergence between RTL, synthesis, and physical design stages for successful tape-out.

What You’ll Do

• Perform RTL-to-Gate and Gate-to-Gate equivalence checks using tools like Cadence Conformal or Synopsys Formality

• Validate low-power design intent (UPF/CPF) and ensure correctness of power-aware transformations

• Debug LEC failures, including issues arising from clock gating, retention, isolation, and level shifters

• Ensure convergence of LEC and CLP across synthesis, place-and-route, and ECO cycles

• Work closely with RTL, Synthesis, DFT, and Physical Design teams to resolve design mismatches

• Handle ECO validation and ensure equivalence closure post-design changes

• Develop automation scripts and improve methodology for LEC/CLP sign-off

What We’re Looking For

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related discipline

• 7+ years of experience in Formal Verification, LEC, and Low Power Verification

• Strong expertise in tools like Cadence Conformal LEC/LP or Synopsys Formality/VC LP

• Solid understanding of low-power design concepts (UPF/CPF), clock gating, power domains

• Experience with synthesis, netlist optimizations, and equivalence debugging

• Proficiency in scripting languages such as TCL, Python, or Perl

Good to Have

• Exposure to advanced low-power techniques (multi-Vt, DVFS, power gating)

• Experience with hierarchical SoC-level LEC/CLP flows

• Familiarity with DFT concepts and scan impact on equivalence

• Knowledge of STA and Physical Design interactions impacting LEC/CLP

Success in This Role Looks Like

• Clean LEC/CLP sign-off with zero functional or power-intent mismatches

• Fast turnaround time in debugging and resolving equivalence issues

• Robust, scalable LEC/CLP methodologies across projects

• Strong cross-team collaboration ensuring smooth design convergence

Location

Hybrid / On-site – Bengaluru